Compressing and expanding operational circuit with no use of clo

Details Compressing and expanding operational circuit with no use of clo Compressing and expanding operational circuit with no use of clo

1993-01-22

1994-05-24

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328169, 328171, 328 31, 328 32, 307494, 307497, 307529, 307264, H03L 500, H03K 501

Patent

active

053152611

ABSTRACT:
An operational circuit without using a clock signal to be used for a compressing or expanding circuit, which comprises a first and second DC signals different in polarity from each other are obtained in response to an input AC signal. The AC signal and a first DC signal are differentially amplified to obtain a first differential output signal, and the AC signal and a second DC signal are differentially amplified to obtain a second differential output signal. A rectified AC signal thus obtained is averaged to obtain an averaged rectified signal as well as to obtain a first and second signals in accordance with the averaged rectified signal. The AC signal and the first signal are differentially amplified to obtain a third differential output signal and the AC signal and the second signal are differentially amplified to obtain a fourth differential output signal. The third and fourth differential output signals are combined so as to be opposite in polarity to take out the product signal of the AC signal and the averaged rectified signal.

REFERENCES:
patent: 4465978 (1984-08-01), Helmstetter
patent: 4812771 (1989-03-01), Lauper et al.
patent: 4920279 (1990-04-01), Charlet et al.
A Sigma-Delta Based Square-Law Compandor, IEEE 1990 Custom Integrated Circuits Conference, by K. Takasuka, et al., pp. 12.7.1-12.7.4.

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