System and method of establishing error precedence in a computer

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3951851, 39518319, 39518509, G06F 1100

Patent

active

057580650

ABSTRACT:
A system and method of establishing error precedence in a computer system which determine a first error to occur. The system determines the order of occurrence of errors in a computer system and includes error precedence modules which record and order errors that occur on a first bus with error that occur on a second bus. Diagnostic processing circuitry reads the errors stored within the error precedence modules and their order of occurrence and determines which bus the first error occurred on.

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Dahbura et al., "An Optimal Test Sequence for the JTAG/IEEE p. 1149.1 Test Access Port Controller", 1989, pp. 55-62, IEEE.

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