Manufacturing a semiconductor integrated circuit device having o

Details Manufacturing a semiconductor integrated circuit device having o Manufacturing a semiconductor integrated circuit device having o

1991-07-31

1993-05-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 8, 437925, H01L 2166

Patent

active

052081788

ABSTRACT:
The present invention relates to a logic correction for a random logic IC of a high integration density, and more particularly to an on-chip logic correction method wherein the upper surface of a chip is divided into a large number of macrocells, testing of the macrocells is made and each defective macrocell is corrected by replacement. Testing is performed after a primary wiring process that connects semiconductor elements into macrocells but before a secondary wiring process interconnecting the macrocells. After the testing, defective macrocells are replaced, and thereafter the secondary wiring process is performed. Testing is performed using testing pads in each macrocell, connected to the main circuit portion of the macrocell through shift register circuit portions. The macrocells are arranged in a lattice pattern. Wirings formed in the secondary wiring process have a larger cross-sectional area than wirings formed in the primary wiring process.

REFERENCES:
patent: 4924589 (1990-05-01), Leedy
patent: 4954453 (1990-09-01), Venutolo
patent: 5037771 (1991-08-01), Lipp
patent: 5039602 (1991-08-01), Merrill et al.
Nikkei Microdevice . . . , Nikkei MacGraw-Hill, pp. 45 and 46, Apr. 1986.
IEEE Journal of Solid-. . . , vol. SC-21, No. 4, Oct. 1986, "Silicon Hybrid Wafer-Scale . . . ", pp. 845-851.

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