Microcomputer system with selectively bypassed memory output lat

Details Microcomputer system with selectively bypassed memory output lat Microcomputer system with selectively bypassed memory output lat

1989-03-20

1992-09-29

Bowler, Alyssa H.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395375, 36518905, 365239, G06F 1300, G06F 1312, G11C 700

Patent

active

051519836

ABSTRACT:
A microcomputer system includes a memory storing various processing data including instruction codes, and a data processor for executing an instruction. The memory includes an address pointer for indicating an address for the memory and supplying the stored address to the memory, and an incrementer for incrementing the address pointer. A latch is coupled to the memory for holding an output of the memory read out in accordance with the address supplied from the address pointer. A bus interface is provided for controlling the address pointer and the incrementer so as to cause a one-time transfer to be performed between the memory and the data processor after an address is supplied from the data processor to the address pointer. The bus interface also controls the address pointer, the incrementer and the latch so that the latch holds contents which are read out from the memory at the address supplied by the address pointer, and the incrementer to increment the address pointer, whereby a continuous transfer is realized between the memory and the data processor without continuously supplying addresses from the data processor.

REFERENCES:
patent: 3969724 (1976-07-01), Anderson et al.
patent: 4280199 (1981-07-01), Osakabe et al.
patent: 4293908 (1981-10-01), Bradley et al.
patent: 4802125 (1989-01-01), Yamada
patent: 4882710 (1989-11-01), Hashimoto et al.

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