Semiconductor memory including an arrangement to permit external

Details Semiconductor memory including an arrangement to permit external Semiconductor memory including an arrangement to permit external

1988-04-25

1992-09-29

Bowler, Alyssa H.

Static information storage and retrieval

Addressing

Sync/clocking

36518903, 36523008, 36518905, 365201, G11C 700, G11C 11412

Patent

active

051518813

ABSTRACT:
A semiconductor memory comprises a memory array including a plurality of memory cells, a peripheral circuit which executes either an information write or read operation with respect to one or more memory cells selected from the plurality of memory cells, a timing control circuit which forms at least one internal control signal for controlling the peripheral circuit, and at least one external terminal for delivering said at least one internal control signal to the outside of the semiconductor memory. For example, the peripheral circuit can include an arrangement to permit the peripheral circuit to operate in a test mode to deliver the internal control signal to the external terminal to allow external testing of the operation of the internal control signal.

REFERENCES:
patent: 4603405 (1986-07-01), Michael
patent: 4608669 (1986-08-01), Klara et al.
patent: 4635233 (1987-01-01), Matsumoto et al.
patent: 4660180 (1987-04-01), Tanimura et al.
patent: 4703453 (1987-10-01), Shinoda et al.
"Hitachi IC Memory Data Book" Hitachi Ltd. Sep. 1983 pp. 251-259.

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