Process for fabricating a graded-channel MOS device

Details Process for fabricating a graded-channel MOS device Process for fabricating a graded-channel MOS device

1995-02-28

1997-02-25

Niebling, John

Fishing, trapping, and vermin destroying

437 44, 257345, H01L 218234

Patent

active

056058551

ABSTRACT:
A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).

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Yoshinori Okumura, "Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Voltage Controllability", IEEE Transactions on Electron Devices, vol. 39, No. 11, Nov. 1992, pp. 2541-2552.

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