Method of fabricating improved lateral Silicon-On-Insulator (SOI

Details Method of fabricating improved lateral Silicon-On-Insulator (SOI Method of fabricating improved lateral Silicon-On-Insulator (SOI

1995-02-27

1996-11-26

Fourson, George

Fishing, trapping, and vermin destroying

437157, 437904, H01L 21265, H01R 2122

Patent

active

055785069

ABSTRACT:
A high performance lateral Silicon-On-Insulator (SOI) power device having a high breakdown voltage (.ltoreq.100 v). The SOI power device includes a silicon layer formed on an oxide layer over a silicon substrate. A mask having a single opening on the anode (drain) side of the silicon layer is formed thereon such that an impurity may be introduced into the silicon layer. The resultant dopant is implanted in the anode side and laterally diffused by high temperature annealing. The resultant device sustains breakdown voltages of up to 100 volts and enables an extremely low on-state resistance of 1.2 milliohm-cm.sup.2.

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Wrathall, R. S., et al. "Charge Controlled 80 Volt Lateral DMOSFET with Very Low Specific On-Resistance Designed for an Integrated Power Process", pp. 32.8.1-32.8.4.

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