Memory device that utilizes single-poly EPROM cells with CMOS co

Details Memory device that utilizes single-poly EPROM cells with CMOS co Memory device that utilizes single-poly EPROM cells with CMOS co

1999-10-26

2000-10-24

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518505, 36518528, G11C 1604

Patent

active

061377244

ABSTRACT:
A memory device is disclosed which includes a plurality of memory cells formed in rows and columns. Each memory cell includes a Frohmann-Bentchkowsky p-channel memory transistor and an n-channel MOS access transistor. A plurality of page lines are utilized to contact each memory transistor, while a plurality of enable lines are utilized to contact each access transistor.

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Frohmann-Bentchkowsky, D., "THAM 7.3: A Fully-Decoded 2048-Bit Electrically-Programmable MOS-ROM," IEEE International Solid-State Circuits Conference, Feb. 18, 1971, Pennsylvania, PA., pp. 80-81; 200.

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