Method of making top buss virtual phase frame interline transfer

Fishing – trapping – and vermin destroying

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437 26, 437 50, H01L 2170

Patent

active

051513803

ABSTRACT:
In one embodiment of the invention, a method for fabricating a virtual phase image sensor is disclosed comprising the steps of forming a semiconductor substrate of a first conductivity type, forming a buried channel region of a second conductivity type in the substrate, forming a virtual gate of the first conductivity type at a surface of the buried channel region, implanting channel stop regions of the first conductivity type in the virtual gate, the channel stop regions contacting the buried channel, and forming a conductive contact on an upper surface of the channel stop regions wherein the conductive contact is additionally coupled to the substrate. In another embodiment of the invention, a method for fabricating a virtual phase image sensor is disclosed comprising the steps of forming a semiconductor substrate of a first conductivity type, forming a buried channel region of a second conductivity type, forming a gate insulator layer on the buried channel, selectively forming a conductive gate region on the gate insulator, depositing and patterning a masking layer on the conductive gate and the gate insulator such that a portion of an edge of the conductive gate and the gate insulator such that a portion of an edge of the at least one conductive gate is exposed by the masking layer pattern, and implanting a channel stop region of the first conductivity type in the buried channel in areas exposed by the masking layer pattern, whereby a side of the channel stop region is self-aligned to the portion of an edge of the conductive gate.

REFERENCES:
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patent: 4642877 (1987-02-01), Garner et al.
patent: 4660090 (1987-04-01), Hynecek
patent: 4668971 (1987-05-01), Hynecek
patent: 4673963 (1987-06-01), Hynecek
patent: 4992392 (1991-02-01), Nichols et al.

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