1979-09-06
1981-07-07
Wojciechowicz, Edward J.
357 34, 357 35, 357 36, 357 46, 357 48, 357 92, H01L 2702
Patent
active
042777941
ABSTRACT:
A structure for logic circuits comprises a current source formed by a PNP transistor and two complementary transistors integrated on the same N-type substrate. A buried plate and P-type walls forms insulating housings. These two complementary transistors are of the vertical type and the PNP transistor has the buried layer as its collector. This buried layer and the insulating walls enable current to be injected into the PNPN structure which eliminates the need for surface interconnection networks and increases the integration density.
REFERENCES:
patent: 4038680 (1977-07-01), Yagi et al.
patent: 4056810 (1977-11-01), Hart et al.
"Thomson-CSF"
Wojciechowicz Edward J.
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