Multi-layer digital circuit board with a test pattern section

Details Multi-layer digital circuit board with a test pattern section Multi-layer digital circuit board with a test pattern section

1994-10-28

1996-03-19

Nguyen, Hoa T.

Excavating

371 27, H04B 1700

Patent

active

055008623

ABSTRACT:
In a digital circuit board comprising a circuit mounting section and a test pattern section, the circuit mounting section has a circuit upper face on which the edge connector and an LSI circuit are mounted. The circuit mounting section has a circuit back face opposite to the circuit upper face. The circuit mounting section has a plurality of terminal through holes, the connector terminals including connector test terminals for use in testing the LSI circuit, and the LSI terminals including LSI test terminals for use in testing the LSI circuit. The terminal through holes have ends connected to the connector test terminals and to the LSI test terminals and have another ends which reach to the circuit back face. The test pattern section has a test upper face which is in contact with the circuit back face and on which test conductive patterns are formed. The test conductive patterns are for use in testing the LSI circuit and connecting the LSI test terminals with the connector test terminals via the terminal through holes. A plurality of LSI circuits may be mounted on the digital circuit board. In the event, the LSI circuit may be both a boundary scan LSI with a boundary scan test logic circuit and an unboundary scan LSI which does not contain the boundary scan test logic circuit.

REFERENCES:
patent: 4150421 (1979-04-01), Nishihara et al.
patent: 4299873 (1981-11-01), Ogihara et al.
patent: 4636919 (1987-01-01), Itakura et al.
patent: 4700016 (1987-10-01), Hitchcock et al.
patent: 4799128 (1989-01-01), Chen
patent: 4873764 (1989-10-01), Grimm
patent: 5399982 (1995-03-01), Driller et al.

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