Conductivity-modulated FET with improved pinch off-ron performan

Details Conductivity-modulated FET with improved pinch off-ron performan Conductivity-modulated FET with improved pinch off-ron performan

1987-10-21

1989-10-10

Carroll, J.

357 20, 357 22, 357 90, H01L 2906, H01L 2980, H01L 2712

Patent

active

048735647

ABSTRACT:
The constraint on the channel thickness of a conductivity-modulated FET is reduced by forming the junction gate region of a pair of differentially doped regions, one inside the other. The first, larger region, which extends from the surface of the island region to a prescribed depth therein, has a lower impurity concentration and higher resistivity, approximating that of the island region in which it is formed. Disposed in a surface portion of this first, high resistivity, low impurity concentration region is a second, relatively shallow, region more heavily doped than the deeper high resistivity region. During the on-condition of the FET, the thickness of the channel is effectively region beneath the low impurity concentration gate region and the semiconductor material of the low impurity concentration gate region beneath the relatively shallow high impurity concentration low resistivity region formed therein. As a result, during the on-condition of the FET, the on-resistance is effectively reduced because of the increased effective channel thickness. In the off state, excess carriers which conductivity-modulate the channel are not present, so that the channel thickness is confined in the island region and the bottom of the channel. This reduced off thickness yields a lower pinch off voltage.

REFERENCES:
patent: 3836998 (1974-09-01), Kocsis et al.
patent: 4187514 (1980-02-01), Tomisawa et al.
patent: 4354121 (1982-10-01), Terasawa et al.
patent: 4514747 (1985-04-01), Miyata et al.
A. S. Grool, Physics and Technology of Semicondensate Process, John Wiley & Sons (1967) pp. 78-82).

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