Memory operations priority scheme for microprocessors

Details Memory operations priority scheme for microprocessors Memory operations priority scheme for microprocessors

1991-06-14

1996-09-03

Elmore, Reba I.

Railway wheels and axles

Axle

Mine car

295478, 364DIG1, G06F 1318

Patent

active

055532683

ABSTRACT:
A structure and a method are provided to implement a memory bus arbiter, in which separate priorities are provided to instruction and data reads from the main memory. In one embodiment in a microprocessor with an on-chip cache, the present invention provides an arbiter which yields the memory bus, in decreasing priority order, to an ongoing bus transaction, a "direct memory access" (DMA) request, an instruction read resulting from a cache miss, a pending write request, and a read request, including reference to an uncacheable portion of memory and a data cache miss.

REFERENCES:
patent: 4067059 (1978-01-01), Derchak
patent: 4829467 (1989-05-01), Ogata
patent: 5057837 (1991-10-01), Colwell et al.
patent: 5193189 (1993-05-01), Flood et al.
patent: 5253348 (1993-10-01), Scalise
patent: 5263142 (1993-11-01), Watkins et al.

Affiliated with

Also associated with

Rating

Memory operations priority scheme for microprocessors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory operations priority scheme for microprocessors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory operations priority scheme for microprocessors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1959461