Workload balancing in a microprocessor for reduced instruction d

Details Workload balancing in a microprocessor for reduced instruction d Workload balancing in a microprocessor for reduced instruction d

1997-12-09

1999-02-09

Lim, Krisna

395386, 395388, 39580023, 39580026, G06F 930

Patent

active

058705783

ABSTRACT:
A microprocessor employs a set of symmetrical functional units, each of which is coupled into an issue position. Instructions are fetched and aligned to the issue positions. During clock cycles in which fewer than the maximum number of instructions are concurrently selected for dispatch to the issue positions, the microprocessor distributes the selected instructions among the issue positions in order to substantially equalize the number of instructions conveyed to each issue position over a number of clock cycles. For example, the microprocessor may employ a counter, each value of which indicates a different set of issue positions to which instruction(s) are to be distributed. The counter is incremented each time the value is used to select a distribution. The resources in each issue position may be used more efficiently due to the more even distribution of instructions among the issue positions.

REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 5053631 (1991-10-01), Perlman et al.
patent: 5058048 (1991-10-01), Gupta et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5136697 (1992-08-01), Johnson
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5371864 (1994-12-01), Chuang
patent: 5377339 (1994-12-01), Saito et al.
patent: 5613080 (1997-03-01), Ray et al.
patent: 5627982 (1997-05-01), Hirata et al.
patent: 5649138 (1997-07-01), Ireton
patent: 5651125 (1997-07-01), Witt et al.
patent: 5748978 (1998-05-01), Narayan et al.
patent: 5751981 (1998-05-01), Witt et al.
patent: 5758114 (1998-05-01), Johnson et al.
Intel, "Chapter 2: Microprocessor Architecture Overview," 1994, pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.
"Intel Architecture Software Developer's Manual, vol. 1: Basic Architecture", Intel Corporation, Prospect IL, 1996, 1997, Chapter 8: Programming With The Intel MMX.TM. Technology, pp. 8-1 through 8-15.
Holstad, S., "Tutorial Tuesday: Decoding MMX" Jan. 14, 1997, Earthlink Network, Inc. copyright 1997, 5 pages (see http://www.earthlink.net/daily/Tuesday/MMX).
"Intel MMX.TM. Technology --Frequently Asked Questions" 6 pages (see http://www.intel.com/drg/mmx/support/faq/htm).

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