Data link module for time division multiplexing control systems

Details Data link module for time division multiplexing control systems Data link module for time division multiplexing control systems

1994-09-13

1996-09-03

Hsu, Alpus H.

Multiplex communications

Wide area network

Packet switching

3701055, 370113, 3408256, H04J 302

Patent

active

055530702

ABSTRACT:
A programmable data link module (32) for use in a time division multiplexing control system (30) having a plurality of modules interconnected by a bus (40) for passing control signals between data link modules on a serial multiplex basis. Each module includes an integrated circuit (80) having signal conditioning circuits (180, 186 and 188) including a programmable hysteresis circuit (126), a power on reset delay circuit (190), a safety input inhibit circuit (220), a clock loss detect circuit (240), a safety output protection circuit (262), a data verifier (260), a polarity selector for a third output terminal (350), an input synchronizer (182 and 184), a combined mode/sync output terminal (110), a multiplex clock output terminal (108), a programming circuit (232) for accepting programming over the clock bus (44) and data bus (46), input/output word extender circuits (104, 106), a high voltage protection circuit (420) including a transistor (600) and a data bus integrity checker (630).

REFERENCES:
patent: 4052566 (1977-10-01), MacKay
patent: 4156112 (1979-05-01), Moreland
patent: 4435706 (1984-03-01), Callan
patent: 4682168 (1987-07-01), Chang et al.
patent: 4808994 (1989-02-01), Riley
patent: 5043911 (1991-08-01), Rashid

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