Eliminating retiming bottlenecks to improve performance of synch

Details Eliminating retiming bottlenecks to improve performance of synch Eliminating retiming bottlenecks to improve performance of synch

1992-11-05

1996-09-03

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364 49D, 364578, 364491, 371 221, 371 223, G06F 1750, G06F 104

Patent

active

055530001

ABSTRACT:
A technique for optimizing the speed of sequential synchronous digital circuits. First, the bottlenecks that prevent retiming for shortening the delay period are identified and then conditions to eliminate the bottlenecks are derived. This involves identifying the subcircuits associated with the bottlenecks, satisfying a set of timing constraints on the subcircuits, and developing a new circuit that meets the timing constraints. The new circuit free of bottlenecks can generally be retimed by relocation of the forward slack latches to reduce the clock period.

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