Planarization and etch back process for semiconductor layers

Details Planarization and etch back process for semiconductor layers Planarization and etch back process for semiconductor layers

1995-04-27

1996-09-03

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437231, 1566431, 1566531, A01L 21311

Patent

active

055523463

ABSTRACT:
An improved process for planarization of an integrated circuit structure having raised portions is provided. A conformal insulating layer is deposited over the structure. Next, a sacrificial dielectric layer is formed over the insulating layer. A planarization layer is formed over the dielectric layer. Then, parts of the planarization layer, dielectric layer, and insulating layer are etched to planarize said integrated circuit structure using an etch chemistry which provides for an uniform etch rate through all three layers. The sacrificial dielectric layer and the etch chemistry provide uniform etching by eliminating micro loading effects.

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`Si Proc For The VLSI Era`, Wolf, Stanley, vol. 2, (1990) Lattice Press.
`Improved Sub-U Inter-Metal . . . TEOS/O.sub.3 APCVD`, p. 22 E. J. Korczynski, Microelectronics Manufacturing Tech. (1992).

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