Time skewing arrangement for operating memory in synchronism wit

Details Time skewing arrangement for operating memory in synchronism wit Time skewing arrangement for operating memory in synchronism wit

1995-06-07

1996-09-24

Heckler, Thomas M.

395494, G06F 110, G06F 1200

Patent

active

055600000

ABSTRACT:
A data processing system includes a plurality of synchronous random access memory devices, a data processor, and a time skewing circuit interposed between the data processor and the plurality of synchronous memory devices. The time skewing circuit imparts different increments of delay time into memory clock and address signals transmitted to different ones of the synchronous memory devices, imparts different increments of delay time into various control signals, and imparts a uniform increment of delay time into several write enable signals. The read enable signals and the write enable signals are used for loading data into data storage devices, which are a part of the time skewing circuit that is interposed between the data processor and the synchronous memory devices.

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