Patent
1994-06-30
1996-09-24
Kim, Matthew M.
395467, 395496, 395473, 395403, G06F 1208
Patent
active
055599877
ABSTRACT:
A method and apparatus in a computer system for updating Duplicate Tag cache status information. The invention operates in a computer system having one or more processor modules coupled to a system bus operating in accordance with a SNOOPING bus protocol. Processor commands and addresses for modification of an entry of the processor's Duplicate Tag status information is provided by the processor to its address interface to the system bus. System bus command and address information is received and stored in a interface pipeline of the address interface. A determination is made as to whether the system bus commands and addresses in the interface pipeline are valid. If there are no valid system bus commands and addresses in the interface pipeline, the Duplicate Tag status information is updated without determining if the processor commands and addresses conflict with the system bus commands and addresses.
REFERENCES:
patent: 4622631 (1986-11-01), Frank et al.
patent: 5148533 (1992-09-01), Joyce et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5226148 (1993-07-01), Milia et al.
patent: 5319766 (1994-06-01), Thaller et al.
Foley Denis
Steinman Maurice B.
VanDoren Stephen R.
Casey Mark J.
Digital Equipment Corporation
Fisher Arthur W.
Kim Matthew M.
Maloney Denis G.
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