Program counter update mechanism

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

3649332, G06F 926

Patent

active

055599753

ABSTRACT:
A processor which includes a fetch program counter circuit and an execute program counter circuit is disclosed. The fetch program counter circuit provides less significant program counter value bits in addition to a fetch program counter value. The execute program counter circuit generates an execute program counter value using the less significant program counter value bits. The execute program counter circuit receives a plurality of less significant program counter bit values and selects a single less significant program counter bit value thus generating execute program counter values in a multiple pipeline processor.

REFERENCES:
patent: 3781808 (1973-12-01), Ahearn et al.
patent: 4044338 (1977-08-01), Wolf
patent: 4155119 (1979-05-01), Ward
patent: 4179737 (1979-12-01), Kim
patent: 4384343 (1983-05-01), Morganti
patent: 4453212 (1984-06-01), Gaither
patent: 4727481 (1988-02-01), Auguille
patent: 4736288 (1988-04-01), Shintani et al.
patent: 4807115 (1989-02-01), Torng
patent: 5056006 (1991-10-01), Acharya et al.
patent: 5131086 (1992-07-01), Circello et al.
patent: 5136697 (1992-08-01), Johnson
patent: 5155816 (1992-10-01), Kohn
patent: 5155820 (1992-10-01), Gibson
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5261063 (1993-11-01), Kohn
patent: 5274790 (1993-12-01), Suzuki
patent: 5325499 (1994-06-01), Kummer et al.
patent: 5404470 (1995-04-01), Miyake
patent: 5450560 (1995-09-01), Bridges et al.
patent: 5465373 (1995-11-01), Kahle et al.
IBM Technical Disclosure Bulletin, vol. 32, No. 5A, Oct. 1989, pp. 33-36, XP 000048827, "Role-Back Interrupt Method for Out-Of-Order Execution of System Programs".
Brian Case, "AMD Unveils First Superscalar 29K Core", Microprocessor Report, Oct. 24, 1984, pp. 23-26.
Michael Slater, "AMD's K5 Designed to Outrun Pentium", Microprocessor Report, Oct. 24, 1994, pp. 1, 6-11.
Toyohiko Yoshida, et al., "The Approach to Multiple Instruction Execution in the GMICRO/400 Processor", IEEE, .COPYRGT.1991, pp. 185-195.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Program counter update mechanism does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Program counter update mechanism, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Program counter update mechanism will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1947483

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.