Method and apparatus for data path circuit layout design and mem

Details Method and apparatus for data path circuit layout design and mem Method and apparatus for data path circuit layout design and mem

1996-02-16

1998-04-07

Teska, Kevin J.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

057372373

ABSTRACT:
The present invention provides a data path circuit layout design method capable of generating a mask layout which satisfies timing specifications and given contour conditions, and which is reduced in circuit area.
There are prepared function macros in each of which there is defined an expansion, according to the parameters, to a circuit comprising a plurality of schematic leaf cells. For a data path circuit of which function blocks are described by function macros, the placement of the function blocks is optimized by a function macro placement process. By a function macro expansion process, the function macros describing the function blocks are expanded and connection information on the schematic leaf cell level are prepared. By a detail placement and routing process, the schematic leaf cells are replaced with the corresponding layout leaf cells and the layout leaf cells are wired to one another, thereby to generate a mask layout of the data path circuit.

REFERENCES:
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 5384710 (1995-01-01), Lam et al.
patent: 5491640 (1996-02-01), Sharma et al.
patent: 5519628 (1996-05-01), Russell et al.
patent: 5555201 (1996-09-01), Dangelo et al.
patent: 5623417 (1997-04-01), Iwasaki et al.
patent: 5625564 (1997-04-01), Rogoyski
patent: 5640328 (1997-06-01), Lam
H. Cai et al., "A Data Path Layout Assembler for High Performance DSP Circuits", 1990, Proceeding of 27th ACM/IEEE Design Automation Conference pp. 306-311, Abstract of this document is described on p. 3 of the Specification.
T. Sakai et al., "Functional Building Block Placement Algorithms for Data-Path Layout", 1992, Research Report of Design Automation Study Group, Information Process Society of Japan, 64-7, pp. 49-56, Abstract of this document is described on p. 3 of the Specification.
H. Nakao et al., "A High Density Layout Generation Method for Datapath Compiler", 1992, Research Report of Design Automation Study Group, Information Process Society of Japan, 63-2, pp. 9-16, Abstract of this document is described on p. 4 of the Specification.
H. Nakao et al., "A High Density Datapath Layout Generation Method Under Path Delay Constraints", 1993, Proceeding of the IEEE 1993 Custom Integrated Circuits Conference, pp. 9.5.1-9.5.5, Abstract of this document is described on p. 4 of the Specification.

Affiliated with

Also associated with

Rating

Method and apparatus for data path circuit layout design and mem does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for data path circuit layout design and mem, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for data path circuit layout design and mem will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-19471