Method of fabricating a bipolar dynamic memory cell

Details Method of fabricating a bipolar dynamic memory cell Method of fabricating a bipolar dynamic memory cell

1981-07-01

1984-10-16

Saba, W. G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576E, 29578, 29580, 148175, 156643, 156649, 357 50, 357 51, 357 92, H01L 21302, H01L 2176

Patent

active

044766238

ABSTRACT:
This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP transistor. By using the PNP transistor as a read transistor and the NPN as a write transistor, the cell, when made in integrated form, utilizes the cell isolation capacitance to enhance the stored information without increasing the parasitic capacitances in the cell. This cell isolation capacitance can be enhanced by trenching between each cell in the array, oxidizing the trench walls and backfilling the trench with semiconductor material thereby obtaining greater contrast between 0 and 1 signals. This cell is especially useful in memory arrays.

REFERENCES:
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patent: 3920482 (1975-11-01), Russell
patent: 3998673 (1976-12-01), Chow
patent: 4084174 (1978-04-01), Crippen et al.
patent: 4256514 (1981-03-01), Pogge
Jambotkar, C. G., "Realization of Large-Valve Capacitance . . . " I.B.M. Tech. Discl. Bull., vol. 21, No.3, Aug. 1978, pp. 1004-1006.

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