Multichannel HDLC framing/deframing machine

Details Multichannel HDLC framing/deframing machine Multichannel HDLC framing/deframing machine

1995-11-30

1997-09-23

Hsu, Alpus H.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370441, 370471, 370474, 370479, H04J 1300, H04Q 1104

Patent

active

056712235

ABSTRACT:
A high speed multichannel HDLC framing machine (112) cycles through Time Division Multiplexed (TDM) channels identifying a channel table (188) for each channel. HDLC state, data to be framed, and a mask are loaded into registers (176, 178), and the framer/deframer (112) is activated. The framer/deframer (112) returns an updated HDLC state, status flags, and a framed code word. The framed code word is multiplexed in a FIFO queue (58) for output on the high speed TDM line (28). A high speed multichannel HDLC deframing machine (112) receives a series of code words from a FIFO queue (56). For each code word received, a corresponding channel table (188) is identified. HDLC state, the code word to be deframed and, a mask are loaded into registers (176, 178), and the framer/deframer (112) is activated. The framer/deframer returns an updated HDLC state, status flags, and potentially a deframed data word.

REFERENCES:
patent: 5375121 (1994-12-01), Nishino et al.
patent: 5459723 (1995-10-01), Thor
patent: 5533018 (1996-07-01), DeJager et al.
patent: 5541919 (1996-07-01), Yong et al.
Published May 1995 by Motorola Inc., "MC68360 Quad Integrated Communications Controller User's Manual", pp. 1-1-11-8.
Published Jul. 1995 by Motorola Inc., "MC68MH360 QUICC32 Quad Integrated Multichannel Controller Reference Manual", pp. 1-1-8-4.

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