Method and apparatus for verifying the design of digital electro

Details Method and apparatus for verifying the design of digital electro Method and apparatus for verifying the design of digital electro

1984-03-22

1987-02-17

Gruber, Felix D.

Boots, shoes, and leggings

371 23, 364488, G06F 1520, G06F 1100, G06G 748

Patent

active

046444874

ABSTRACT:
A method for verifying the design of a digital electronic component in which the component is replaced by a simulation unit connected to the intended host system. The simulation unit has a memory for holding responses to stimuli from the host system. If the required response is not in the memory, it is calculated and placed in the memory, and the operation of the host system is then re-started from the beginning. In this way, the required set of responses is built up incrementally in the memory until, eventually, the operation of the host system can run to completion.

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patent: 4456994 (1984-06-01), Segarra
patent: 4527249 (1985-07-01), Van Brunt
patent: 4590581 (1986-05-01), Widdoes, Jr.

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