Boots – shoes – and leggings
Patent
1984-12-04
1987-02-17
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 938
Patent
active
046444661
ABSTRACT:
A pipeline processor has a plurality of operand registers, a pipelined arithmetic unit, and a plurality of data buses connected between outputs of operational stages of the arithmetic unit and the inputs of the arithmetic unit. A selector is provided for selecting either outputs of the plurality of operand registers or outputs of the operational stages of the arithmetic unit as inputs to the arithmetic unit. The processor further includes a generator for generating operand determination signals indicating that an output of the plurality of operational stages of the arithmetic unit has been determined as write-in data for an operand register corresponding to a stage of the arithmetic unit and a circuit for transmitting and circulating a register number given for the operand register whose renewal is specified by a given instruction. The processor further includes a control circuit responsive to at least the register number and operand determination signal for controlling the selector so as to select at least one of the operand registers when at least one operand for the instruction is held in the at least one operand register. The selector selects the arithmetic unit when the operand for the instruction has already been determined in the arithmetic unit and selects the arithmetic unit after the operand for the instruction has been determined, unless the operand for the instruction is determined such that the operand is supplied to the arithmetic unit.
REFERENCES:
patent: 4454578 (1984-06-01), Matsumoto et al.
patent: 4476525 (1984-10-01), Ishii
NEC Corporation
Zache Raulfe B.
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