Pulse generator having controlled delay to control duty cycle

Details Pulse generator having controlled delay to control duty cycle Pulse generator having controlled delay to control duty cycle

1995-09-15

1996-09-24

Grimm, Siegfried H.

Oscillators

With distributed parameter resonator

Tube enclosed by resonator structure

327175, 327171, 331 34, 331 45, 331 60, 331 75, 331177R, H03B 502, H03K 3017, H03L 7099

Patent

active

055594778

ABSTRACT:
Five CMOS inverters are connected in a series ring to form an oscillator. Current to the inverters is controlled to establish gate delays of the inverters and thereby determine a frequency of oscillation of the oscillator. The oscillator is included in a phase locked loop where the gate delay of the inverters is selected by selecting the value of a frequency divider of the phase locked loop. The selected delay is used to form a train of pulses with a desired duty cycle.

REFERENCES:
patent: 4797585 (1989-01-01), Segawa et al.
patent: 5039893 (1991-08-01), Tomisawa
patent: 5061907 (1991-10-01), Rasmussen
patent: 5068628 (1991-11-01), Ghoshal
patent: 5119045 (1992-06-01), Sato
patent: 5136260 (1992-08-01), Yousefi-Elezei
patent: 5175452 (1992-12-01), Lupi et al.
patent: 5231313 (1993-07-01), Itoh
patent: 5302919 (1994-04-01), Abe
patent: 5302920 (1994-04-01), Bitting
patent: 5347232 (1994-09-01), Nishimichi

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