Semiconductor memory device and manufacturing method for the sam

Details Semiconductor memory device and manufacturing method for the sam Semiconductor memory device and manufacturing method for the sam

1988-02-24

1990-01-30

Hille, Rolf

357 55, 357 41, H01L 2978, H01L 2906, H01L 2902

Patent

active

048977020

ABSTRACT:
An isolated region in which a MOS transistor and a capacitor are formed is surrounded by a groove. The groove includes first and second region grooves. A first insulating layer which separates the isolated region is provided on the inner surface of a predetermined lower portion of the first region groove and on the inner surface of the second region groove. A second insulating layer is provided on the inner surface of the remaining upper portion of the first region groove. The first insulating layer is thinner than half the width of the groove and thicker than the first insulating layer. A capacitor electrode is embedded in the first and second region grooves.

REFERENCES:
patent: 4643804 (1987-02-01), Lynch et al.
Technical Digest of IEDM, "A High Density 4M DRAM Process Using Folded Bitline Adaptive Side-Wall Isolated Capacitor (FASIC) Cell", M. Nagatomo et al.; 1986, pp. 144-147.

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