Complementary MOS integrated circuit including lock-up preventio

Details Complementary MOS integrated circuit including lock-up preventio Complementary MOS integrated circuit including lock-up preventio

1985-08-26

1987-08-25

James, Andrew J.

357 41, 357 44, H01L 2702

Patent

active

046896538

ABSTRACT:
In a complementary MOS-IC (CMOSIC) comprising a p-channel MOS transistor with an n-channel MOS transistor serially connected thereto, a third diffusion layer is provided being of a conductivity type similar to that of the drains of the respective transistors. This third diffusion layer produces a plurality of parasitic bipolar transistors which limit the gain of the naturally occurring parasitic transistors in the CMOSIC. By limiting the gain, the third diffusion layer drastically reduces the chance of CMOSIC breakdown upon the occurence of high input transients.

REFERENCES:
patent: 3573509 (1971-04-01), Crawford
patent: 3955210 (1976-05-01), Bhatia et al.
patent: 4173767 (1979-11-01), Stevenson
patent: 4327368 (1982-04-01), Uchida

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