Dividing apparatus

Details Dividing apparatus Dividing apparatus

1984-12-27

1988-06-28

Harkcom, Gary V.

Boots, shoes, and leggings

364764, 364787, G06F 752, G05F 750

Patent

active

047544228

ABSTRACT:
A high-speed dividing apparatus includes a first, second and third carry save adders (CSA's) and the outputs of the first CSA are connected to the inputs of the second and third CSA's. The first CSA is capable of carrying out either the addition or the subtraction of a divisor. The second CSA is adapted to carry out the subtraction of a divisor, and the third CSA the addition thereof. A carry look-ahead logic is connected to each CSA. A quotient determining logic is adapted to determine quotient bits in response to outputs from CSA's and carry look-ahead logics. A selector control logic is adapted to control selectors in response to quotient bits so that outputs from one of the second and third CSA's and either a divisor or the complement thereof are selectively supplied to the inputs of the first CSA. An arbitrary number of stages can be arranged in a binary tree configuration in the same manner.

REFERENCES:
patent: 3234367 (1966-02-01), Ottaway et al.
patent: 3873820 (1975-03-01), Parr et al.
patent: 4337519 (1982-06-01), Nishimoto
patent: 4488247 (1984-12-01), Inagami et al.
patent: 4549280 (1985-10-01), Schomburg
Bratun et al., Multiply/Divide Unit for a High-Performance Digital Computer, Nov. 1971, IBM Technical Disclosure Bulletin, vol. 14, No. 6, pp. 1813-1816.
K. G. Tan, Uniform 2 Bits Quotients Binary Division by Carry-Save Adders, IBM Technical Disclosure Bulletin, vol. 14, No. 11, Apr. 1972, pp. 3279-3281.

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