Display deflection control loop

Details Display deflection control loop Display deflection control loop

1987-07-22

1988-06-28

Masinick, Michael A.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358148, H04N 504

Patent

active

047543302

ABSTRACT:
A system for synchronizing a succession of horizontal deflection coil currents of a CRT display with a succession of synchronization signals includes a variable delay which is strobed by a synchronization signal and triggers the generation of a deflection current after a specified delay. The delay is automatically controlled by a feedback loop in which the present delay is measured by a set-reset flip-flop, the flip-flop providing an output pulse having a duration equal to the delay. An integrator averages a train of output pulses from the flip-flop, and combines a reference signal with the average value to provide the control signal for the delay. The system operates with minimal bandwidth and with dynamics which are free of acquisition constraints so as to provide minimal sensitity to noise.

REFERENCES:
patent: 3821470 (1974-06-01), Merrell
patent: 3891800 (1975-06-01), Janssen et al.
patent: 4228463 (1980-10-01), Steckler et al.
patent: 4253117 (1981-02-01), Kadlec
patent: 4317133 (1982-02-01), Fernsler
patent: 4396948 (1983-08-01), Fernsler
patent: 4467359 (1984-08-01), Hosoya

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