Serial encoding-decoding for cyclic block codes

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G06F 1110

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043120695

ABSTRACT:
Means for serially encoding and decoding cyclic block codes having minimal parity check bits and single error correcting capability are disclosed.
Encoder (12) comprises: serial shift and divide means (4100, 4150, 4200, SA, S3, S4 and S5) for generating parity check bits to append to the data word and thereby form the channel word; input buffer (4300) for storing bits of the next channel word during evaluation of the parity bits of the previous word; and output buffer registers (4400 through 4800) for storing bits of the channel word for eventual transmission. Certain registers (4400 through 4800) are partitioned into a parallel arrangement of register segments of predetermined lengths so as to effect full loading of each segmented register prior to the request for transmission from each register.
Decoder (20) comprises: means (5100, 5200, 5030, SA1, SB1, or 6100, 6200, 6030, SA2, SB2) for shifting and dividing the received word to generate the syndrome as well as iteratively shifted versions of the syndrome; means (5300,5031 or 6300,6301), alternating operation with the shifting and dividing means, for comparing the characteristic polynomial (5300) of the code with the iteratively shifted versions of the syndrome; and means (5020, 5021, 5022 and 5400 or 6400) for correcting, in response to a predetermined output from the comparing means, the received word by inverting the bit in the received word depending on the number of iterations performed in generating the iteratively shifted versions of the abstract. The decoder comprises two substantially identical sections each having two modes of operations. The sections alternate modes of operation so that two contiguous blocks are processed during a given interval.

REFERENCES:
patent: 3568148 (1971-02-01), Clark, Jr.
patent: 3774153 (1973-11-01), Ahamed
patent: 3944973 (1976-03-01), Masson
patent: 3983536 (1976-09-01), Telfer
Ahamed, "The Design & Embodiment of Magnetic Domain Encoders & Single-Error Correcting Decoders for Cyclic Block Codes", The Bell System Technical Journal, vol. 51, No. 2, Feb. 1972, pp. 461-485.
Cummins, "Displacement Calculation of Error Correcting Syndrome Bytes by Table Lookup", IBM Technical Disclosure Bulletin, vol. 22, No. 8B, Jan. 1980, pp. 3809-3810.

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