Method of manufacturing semiconductor memory device

Details Method of manufacturing semiconductor memory device Method of manufacturing semiconductor memory device

1989-12-15

1991-09-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 48, 437 49, 437 50, 437 52, 437191, 437195, 437233, 437235, H01L 21336

Patent

active

050495160

ABSTRACT:
An EEPROM formed of three-layer polysilicon is provided. A floating gate is at a second level and a portion thereof is at a first level. A first control gate and a select gate are formed spaced against from each other at the first level and a portion of the second floating gate extends between them for formation of a tunnel region. A second control gate which is kept at the same potential as the first control gate exist at a third level. In this EEPROM, electrons are drawn from the floating gate by applying a high voltage to the select gate.

REFERENCES:
patent: 4307411 (1981-12-01), Carnes et al.
patent: 4355375 (1982-10-01), Arakawa
patent: 4417264 (1983-11-01), Angle
patent: 4425631 (1984-10-01), Adam
patent: 4513397 (1985-04-01), Ipri et al.
patent: 4618876 (1986-10-01), Stewart et al.

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