1996-11-20
2000-02-15
Teska, Kevin J.
39550009, 39550012, G06F 1750
Patent
active
060262249
ABSTRACT:
A wiring design tool which detects minimum area vias and replaces them with redundant vias pairs. The invention uses the definitions for single vias and tracks in a grid coordinate system and a file describing the design wires and their interconnections to select the most favorable direction for the placement. The invention accomplishes this by examining the directions one track away from each single via at various levels and according to the methodology of this invention, detects a possible situs for a redundant via pair, preferably where a segment of wire on the same net already exists. If no design rule violation occurs the system replaces the single via with a redundant via pair.
REFERENCES:
patent: 4831725 (1989-05-01), Dunham et al.
patent: 5124273 (1992-06-01), Minami
patent: 5165166 (1992-11-01), Carey
patent: 5448496 (1995-09-01), Butts et al.
patent: 5798937 (1998-08-01), Bracha
IBM Invention Disclosure, Algorithms For Automatically Improving Yeild and Reliability in VLSI Designs Assembled By Programs, Dec. 1991.
Darden Laura Rohwedder
Livingstone William John
Panner Jeannie Harrigan
Perry Patrick Edward
Pokorny William Frank
Do Thuan
International Business Machines - Corporation
Kotulak Richard M.
Teska Kevin J.
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