Method and apparatus for incremntally optimizing a circuit desig

Details Method and apparatus for incremntally optimizing a circuit desig Method and apparatus for incremntally optimizing a circuit desig

1996-11-19

2000-02-15

Teska, Kevin J.

39550011, G06F 1750

Patent

active

060262206

ABSTRACT:
A method and apparatus for incrementally optimizing a circuit design. The present invention provides an iterative EDA process that only requires the optimization, placement and routing of the actual changes made during a each design iteration, and leaves the remainder of the circuit design in a fixed state.

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