Semiconductor device with wiring layer using bias sputtering

Details Semiconductor device with wiring layer using bias sputtering Semiconductor device with wiring layer using bias sputtering

1987-11-24

1988-12-20

James, Andrew J.

357 65, 357 68, H01L 2348

Patent

active

047928425

ABSTRACT:
Disclosed is a semiconductor device and method for manufacturing the same, which is provided with a first wiring layer whose thickness within a contact hole is great in a lower portion of the contact hole and is small in an upper portion thereof. Since the first wiring layer at the lower portion of the contact hole is sufficiently thick, reaction between a second wiring layer formed on the first wiring layer and a substrate is effectively prevented. The first wiring layer is formed by bias sputtering in which a bias voltage is applied to the substrate.

REFERENCES:
patent: 4158613 (1979-06-01), Sogo
patent: 4161430 (1979-07-01), Sogo
patent: 4271424 (1981-06-01), Inayoshi et al.
Reuitz et al., "Metallurgy Barrier for Au and Pb," IBM Technical Disclosure Bulletin, vol. 14, No. 11, Apr. 1972, p. 3358.
Chapman, "Fabricating Ohmic Contacts," IBM Technical Disclosure Bulletin, vol. 9, No. 4, Sep. 1966, pp. 431-431.
Ting, "Tin Formed by Evaporation as a Diffusion Barrier Between Al and Si", J. Vac. Sci. Technol., 21(1) May/Jun. 1982, pp. 14-18.

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