Television receiver

Details Television receiver Television receiver

1988-09-23

1989-09-26

Peng, John K.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358242, 315387, H04N 504, H04N 568

Patent

active

048704903

ABSTRACT:
In a television receiver including a digital circuit processing an input video signal in a digital mode, a clock generating circuit applies a system clock signal to the digital circuit, and comprises a phase comparator to which a horizontal synchronizing signal is applied, a low-pass filter connected to the phase comparator, a voltage controlled oscillator connected to the low-pass filter to generate the system clock signal, a first frequency divider dividing the frequency of the system clock signal generated from the voltage controlled oscillator to generate a horizontal deflection drive pulse signal, and a second frequency divider connected to the phase comparator. The phase comparator, the low-pass filter, the voltage controlled oscillator, the first frequency divider and the second frequency divider constitute a single PLL circuit, and the system clock signal and the horizontal deflection drive pulse signal are respectively generated from the PLL circuit.

REFERENCES:
patent: 3821470 (1974-06-01), Merrell
patent: 4096328 (1978-06-01), Tuma et al.
patent: 4245251 (1981-11-01), Steckler et al.
patent: 4520394 (1985-05-01), Kaneko
patent: 4591910 (1986-05-01), Lai et al.
patent: 4636861 (1987-01-01), Willis
patent: 4729024 (1988-03-01), Kawai et al.
patent: 4754330 (1988-06-01), Spieth
patent: 4769705 (1988-09-01), Lendaro
patent: 4791488 (1988-12-01), Fukazawa et al.

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