Algebraic coder-decoder for Reed Solomon and BCH block codes, ap

Details Algebraic coder-decoder for Reed Solomon and BCH block codes, ap Algebraic coder-decoder for Reed Solomon and BCH block codes, ap

1987-10-27

1989-12-19

Smith, Jerry

Excavating

G06F 1110

Patent

active

048887781

ABSTRACT:
An algebraic coder-decoder for Reed Solomon and BCH block codes is provided, namely a coprocessor of standard microprocessors specialized for algebraic processing in Galois bodies. This processor includes a clock generator which sets the rhythm of the circuit through a cycle clock and a subcycle clock, a control circuit which integrates an automatic loop system and a cycle stealing device, an arithmetic operator for carrying out simple operations on unsigned numbers representing the variables and the parameters of the algorithms a Galois operator for effecting the elementary polynomial operations in the five Galois bodies and storing the data exchanged with the host processor, an interface circuit which integrates a data exchange managament automation, a data bus, an instruction and the connections required for the control signals which connect the four blocks of the device together.

REFERENCES:
patent: 3533067 (1970-10-01), Zierler et al.
patent: 4142174 (1979-02-01), Chen
patent: 4162480 (1979-07-01), Berlekamp
patent: 4360916 (1982-11-01), Kustedjo
patent: 4637021 (1987-01-01), Shenton
patent: 4649541 (1987-03-01), Lahmeyer
patent: 4715036 (1987-12-01), Oakes
IEEE Transactions on Computers, vol. C-34, No. 8, Aug. 1985, pp. 709-717, "VLSI Architectures for Computing Multiplications and Inverses in GF(2.sup.m)".
Proceedings of SPIE--The International Society for Optical Engineering, vol. 421, "Optical Disks Systems and Applications", E. V. LaBudde, Jun. 8-9, 1983, pp. 65-78.

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