Digital loop carrier system having programmable timeslot and ban

Details Digital loop carrier system having programmable timeslot and ban Digital loop carrier system having programmable timeslot and ban

1988-08-22

1989-12-19

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 851, 34082551, H04J 316

Patent

active

048887650

ABSTRACT:
A system for allocating a plurality of channel units to a transmission line having a plurality of timeslots including bandwidth and multiple time slot allocation. The system has a counter and a parallel to serial register for providing a channel address via an address signal corresponding to a predetermined one of the plurality of timeslots to each of the channel units. A processor is provided for assigning an assigned address to each channel unit of the plurality of channel units, such channel unit being assigned to a different selected timeslot of the plurality of timeslots. Each of the channel units has a comparator for comparing the channel address in the address signal to the assigned address, the channel unit upon having a correspondence between the channel address and the assigned address, transmitting and receiving on the transmission line. A bus connects the plurality of channel units to the means for addressing. An active channel unit can retain control of the transmission line for bandwidth and multiple time slot allocation.

REFERENCES:
patent: 4470140 (1984-09-01), Coffey
patent: 4680583 (1987-07-01), Grover
patent: 4701908 (1987-10-01), Ikeda
patent: 4733390 (1988-03-01), Shirakawa et al.
patent: 4760573 (1988-07-01), Calvignac et al.

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