Memory system for microprocessor with multiplexed address/data b

Details Memory system for microprocessor with multiplexed address/data b Memory system for microprocessor with multiplexed address/data b

1979-10-09

1981-12-15

Zache, Raulfe B.

Boots, shoes, and leggings

365230, G11C 800

Patent

active

043062989

ABSTRACT:
A memory system for a digital processor device having a 16-bit bidirectional bus with multiplexed addresses and data employs separate memory devices for the high order and low order data bytes. When less than 64 K words of memory are used, there are unused address lines in the bus. A microcomputer may use memory devices partitioned 4 K.times.8, needing 12 address pins. Both devices are constructed the same, but one accesses the low order byte and the other the high order byte under control of a single byte-select terminal. Mapping of the bus to memory device connections and internal connection of unused pins to address inputs or data input/output lines within the memory devices, along with the byte-select function, allow a single type of device to function in either position.

REFERENCES:
patent: 3686640 (1972-08-01), Andersen et al.
patent: 3965459 (1976-06-01), Spencer et al.
patent: 3967251 (1976-06-01), Levine
patent: 4091456 (1978-05-01), Ehresman et al.

Affiliated with

Also associated with

Rating

Memory system for microprocessor with multiplexed address/data b does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory system for microprocessor with multiplexed address/data b, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory system for microprocessor with multiplexed address/data b will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1907083