Hit/miss logic for a cache memory

Details Hit/miss logic for a cache memory Hit/miss logic for a cache memory

1980-12-31

1982-12-07

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 1300

Patent

active

043630952

ABSTRACT:
In a data processing system a cache memory comprises level one and level two even and odd data stores and level one and level two even and odd directory stores. The directory stores include a plurality of storage locations for storing the most significant bits of the address numbers associated with the data words stored in the level one and level two even and odd data stores. The level one and level two even and odd directory stores are addressed by the least significant bits of the address numbers. Comparator circuits compare the high order bits of an address number supplied in a memory request to the high order bits stored in the level one even and odd directory stores at storage locations identified by both the low order bits of the address supplied in the memory request and the low order address bits incremented by one. A hit detector circuit determines whether one, both, or none of the requested words are stored in the cache memory by analyzing the outputs of the comparators.

REFERENCES:
patent: 3218611 (1965-11-01), Kilburn et al.
patent: 4055851 (1977-10-01), Jenkins et al.
patent: 4208716 (1980-06-01), Porter et al.
patent: 4212058 (1980-07-01), Gunawardena

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