Method for planarizing a semiconductor topography using a spin-o

Details Method for planarizing a semiconductor topography using a spin-o Method for planarizing a semiconductor topography using a spin-o

1994-06-03

1996-05-14

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437231, 1566361, H01L 21304, H01L 213105, H01L 21316

Patent

active

055167292

ABSTRACT:
A method is provided for forming a planarization structure of dielectrical materials upon a substrate topography. The dielectric materials are deposited as first and second insulating layers. The second, and then the first insulating layers are partially removed by chemical-mechanical polish (CMP). Prior to CMP, the second insulating layer of variable chemical and mechanical properties can be fixed at a preferred chemical or mechanical characteristic which makes it more or less susceptible to subsequent CMP. Accordingly, the present invention utilizes a second insulating layer of adjustable properties necessary to more adequately planarize during application of CMP.

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