Stress relaxation in dielectric before metallization

Details Stress relaxation in dielectric before metallization Stress relaxation in dielectric before metallization

1994-02-14

1996-05-14

Thomas, Tom

Fishing, trapping, and vermin destroying

437927, 148DIG73, H01L 2131

Patent

active

055167209

ABSTRACT:
A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Successive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide. The silicon nitride spacers are removed leaving trenches between the thin silicon dioxide sidewalls and the silicon dioxide spacers. A thin insulating material is deposited over the surface of the gate electrodes and the sidewalls with a step coverage such that the trenches between the thin oxidation and the silicon dioxide spacers are not filled by the thin insulating layer but are covered by the thin insulating layer leaving voids which complete the thermal stress released polysilicon gate spacer formation in the fabrication of an integrated circuit.

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Translation of JP 3-229443 (Saito).

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