Method of forming a transistor

Details Method of forming a transistor Method of forming a transistor

1994-11-10

1996-05-14

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437203, 437228, H01L 21265

Patent

active

055167101

ABSTRACT:
A method is provided for forming a transistor for a bipolar, CMOS, or bipolar CMOS integrated circuit. The method is applicable to forming a double polysilicon self-aligned bipolar transistor using a single masking step for defining the emitter structure with a narrow emitter-base contact area and a large emitter contact area. The method comprises selectively providing a tapered body of dielectric to mask a region of the substrate on which an emitter is to be formed. A conductive layer is provided around the tapered body to form base contact electrodes. The tapered body is selectively removed from the substrate without damaging the underlying silicon substrate, to leave a tapered opening; localized dielectric isolation is provided in the form of sidewall spacers on the first conductive layer. The tapered opening is filled with a layer of a second conductive material to form a second electrode i.e. an emitter structure. The resulting structure is fully planarized, preferably by chemical mechanical polishing, to form coplanar contact areas to the base and emitter.

REFERENCES:
patent: 4440804 (1984-04-01), Milgram
patent: 4774204 (1988-09-01), Havemann
patent: 4892835 (1990-01-01), Rabinzohn et al.
patent: 4983531 (1991-01-01), Cosentino
patent: 4996581 (1991-02-01), Hamasaki
patent: 5034351 (1991-07-01), Sun et al.
patent: 5064774 (1991-11-01), Pfiester
patent: 5155053 (1992-10-01), Atkinson
patent: 5194926 (1993-03-01), Hayden
patent: 5286661 (1994-02-01), Fresart et al.
patent: 5288660 (1994-02-01), Hua et al.
patent: 5302535 (1994-04-01), Imai et al.
patent: 5320972 (1994-06-01), Wylie
J. H. Comfort et al "Profile leverage in a self-aligned epitaxial Si or SiGe Base Bipolar Technology" 1990 IEEE IEDM 90-21, p. 2.4.1.
"A High Speed Bipolar LSI Process Using Self-Aligned Double Diffusion Polysilicon Technology" K. Kikuchi et al IEDM Abstracts p. 420, 1986.
"Sub-30ps ECL Circults Using High-fr Si and SiGe Epitaxial Base SEEW Transistors" J. N. Burghartz et al 1990 IEEE IEDM 90-297 pp. 12.1.1-12.1.4.
"A Sub-30psec Si Bipolar LSI Technology" T. Gomi et al 1988 IEEE IEDM 88 pp. 744-747.

Affiliated with

Also associated with

Rating

Method of forming a transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1895385