High speed multiplex switch circuit and method

Details High speed multiplex switch circuit and method High speed multiplex switch circuit and method

1991-03-19

1992-02-25

Pascal, Robert J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307571, 307572, H03K 1700

Patent

active

050916572

ABSTRACT:
A high speed, high current analog switching circuit includes a switch JFET having its drain electrode connected to an analog input voltage terminal and a source electrode connected to an analog output voltage terminal. The gate electrode of the JFET switch is connected to switching control circuitry. The analog switching circuit includes circuitry that prevents the source-gate PN junction of the switch JFET from ever being forward biased more than approximately 0.2 volts. This prevents the charge storage capacitance of that PN junction from ever increasing to such high values (e.g. 100 to 1000 picofarads) that discharging of the charge storage capacitance through the channel resistance of the switch JFET takes excessively long periods of time. Rapid equalization of the analog output voltage and analog input voltage to within approximately 10 microvolts of each other is thereby achieved.

REFERENCES:
patent: 4042836 (1977-08-01), Compton et al.
patent: 4228367 (1980-10-01), Brown

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