EEPROM memory cell and driving circuitry

Details EEPROM memory cell and driving circuitry EEPROM memory cell and driving circuitry

1988-11-21

1990-07-03

James, Andrew J.

357 234, 357 239, 357 54, H01L 2978, H01L 2934

Patent

active

049395580

ABSTRACT:
An electrically eraseable programmable memory device which includes a floating gate, heavily doped source and drain regions in which one side thereof is laterally spaced from the floating gate, and the other side has a lightly doped "reach-through" region between the heavily doped region and the channel that underlies the floating gate. A control gate overlies the floating gate. The oxide thickness between the gate and channel is sufficiently thin such that electron tunneling takes place between the floating gate and the "reach through" region.

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