VLSI circuits designed for testability and methods for producing

Details VLSI circuits designed for testability and methods for producing VLSI circuits designed for testability and methods for producing

1993-09-20

1995-10-24

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, 364491, H01L 2182

Patent

active

054615739

ABSTRACT:
A VLSI circuit including memory is viewed as a finite state object machine and for testability a finite state test machine is embedded in the finite state object machine. To make the embedding practiced, the object test machine is partitioned into components and separate test machines are embedded into each component. The augmented components are then interconnected to form a composite machine for testing. To have the same test generation complexity as the object machine with a single embedded test function, there are special relations that have to be satisfied in the manner in which the test machines are embedded.

REFERENCES:
patent: 5132974 (1992-07-01), Rosaks
patent: 5222030 (1993-06-01), Dangelo et al.
patent: 5228040 (1993-07-01), Agrawal et al.
patent: 5257268 (1993-10-01), Agrawal et al.
patent: 5321277 (1994-06-01), Sparks et al.

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