Layout pattern verification apparatus

Details Layout pattern verification apparatus Layout pattern verification apparatus

1993-05-25

1995-10-24

Trans, Vincent N.

Boots, shoes, and leggings

364578, G06F 1750

Patent

active

054615720

ABSTRACT:
A layout pattern verification apparatus which can automatically verify surge breakdown resistance. An input resistance verification module (3), an input resistance contact verification module (4) and an input resistance periphery verification module (5) incorporate an input resistance verification rule (55) and layout information (57) provided with input/output information, verify surge breakdown resistance on an input resistance itself, an input resistance contact region and the input resistance and its peripheral region, and output verification result information to a verification result output module (6). It is possible to automatically verify surge breakdown resistance with attention being drawn to a layout pattern of the input resistance causing surge breakdown.

REFERENCES:
patent: 5062054 (1991-10-01), Kawakani et al.
patent: 5198986 (1993-03-01), Ikeda et al.
patent: 5202841 (1993-04-01), Tani
patent: 5359534 (1994-10-01), Iujiki et al
"Resistance Extraction in a Hierarchical IC At Work Verification System", by Mori et al., IEEE 1985, pp. 196-198.
"LAS: Layout Pattern Analysis System with New Approach", by Okamura et al, IEEE 1982, pp. 308-311.

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