Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1992-07-06
1992-12-29
Wojciechowicz, Edward J.
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
437 63, 437141, 437193, 437247, 257518, H01L 2702
Patent
active
051756072
ABSTRACT:
A p-type polycrystalline silicon layer (45) serving as the base electrode of an npn transistor and a p-type polycrystalline silicon layer (50) serving as the emitter electrode of a pnp transistor are simultaneously formed by forming a p-type polycrystalline silicon on the entire surface and patterning the same. Similarly, an n-type polycrystalline silicon layer (46) serving as the emitter electrode of the npn transistor and an n-type polycrystalline silicon layer (49) serving as the base electrode of the pnp transistor are simultaneously formed by forming an n-type polycrystalline silicon on the entire surface and patterning the same. Thus, electrodes can be formed without selective impurity implantation and the mask alignment therefor.
REFERENCES:
K. Toh et al., "A 23ps/2.1mW ECL Gate", ISSCC 89 Digest of Technical Papers, 1989, pp. 224-225.
C. Sung et al., "A 76 MHz Programmable Logic Sequencer", ISSCC 89 Digest of Technical Papers, 1989, pp. 118`119.
Mitsubishi Denki & Kabushiki Kaisha
Wojciechowicz Edward J.
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