High speed system for threshold matrix alignment and tiling, dur

Details High speed system for threshold matrix alignment and tiling, dur High speed system for threshold matrix alignment and tiling, dur

1996-03-04

1998-07-14

Moore, David K.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358458, 358528, H04N 140

Patent

active

057813086

ABSTRACT:
A system converts a source image into destination image pixels that are binary. The system includes a memory which stores at least a portion of a row of source grey level pixels, and a corresponding row of a threshold matrix of plural rows of grey level pixel values, each row including at least W pixel values. A scale register stores N source grey level pixel values that have been scaled to match N grey level destination image pixel locations. A threshold register outputs, in parallel, up to N of the W threshold pixel values. Alignment logic controllably enters the threshold pixel values into the threshold register. A controller operates the alignment logic to enter the W threshold pixel values into N contiguous storage positions in the threshold register, and if W greater than N, enables entry of excess ones of the W threshold pixel values into contiguous storage positions in the threshold register after the (W-N) previously entered threshold pixel values have been outputted. A comparator compares the N source pixel values with corresponding ones of the N threshold pixel values and assigns N binary values to the destination image in accordance with the comparing action.

REFERENCES:
patent: 4246614 (1981-01-01), Knox
patent: 5124803 (1992-06-01), Troxel
patent: 5297289 (1994-03-01), Mintzer
patent: 5305118 (1994-04-01), Schiller et al.
patent: 5422742 (1995-06-01), Ostromoukhov et al.
patent: 5438431 (1995-08-01), Ostromoukhov
patent: 5526445 (1996-06-01), Smutek et al.

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