Two step etch back spin-on-glass process for semiconductor plana

Details Two step etch back spin-on-glass process for semiconductor plana Two step etch back spin-on-glass process for semiconductor plana

1994-06-13

1995-10-24

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437195, 437229, 437231, 437235, 1566431, 1566331, 1566281, 1566311, 1566531, H01L 21465

Patent

active

054610109

ABSTRACT:
A new method for forming a planarized dielectric layer on a patterned conducting layer was accomplished. The method involves forming a insulating layer over a semiconductor substrate having semiconductor devices and elevated areas, created by an array of DRAM storage cells, formed therein. A metal conducting layer is deposited and then patterned by etching. The patterned conducting layer is used to make the electrical connections to the device contact. A barrier insulator is deposited on the patterned conducting layer and then a spin-on-glass is deposited by several coatings to fill the recesses in the patterned conducting layer and planarize the surface. A two step etch back process is then used to further planarize the layer and remove the spin-on-glass from the conducting layer surface. The process is designed to avoid over etching into the patterned conducting layer at the edges of the elevated regions of the DRAM, where the spin-on-glass is by its very nature thin.

REFERENCES:
patent: 4826786 (1989-05-01), Merenda et al.
patent: 4894351 (1990-01-01), Batty
patent: 4952274 (1990-08-01), Abraham
patent: 4983546 (1991-01-01), Hyun et al.
patent: 4986878 (1991-01-01), Malazgirt et al.
patent: 5003062 (1991-03-01), Yen
patent: 5173151 (1992-12-01), Namose
patent: 5266525 (1993-11-01), Morozumi
patent: 5268244 (1993-12-01), Yoo
patent: 5294294 (1994-03-01), Namose
patent: 5296092 (1994-03-01), Kim
patent: 5316980 (1994-05-01), Takeshiro
patent: 5350486 (1994-09-01), Huang
patent: 5376435 (1994-12-01), Morozumi
patent: 5378318 (1995-01-01), Weling et al.
patent: 5391259 (1995-02-01), Cathey et al.
patent: 5401998 (1995-03-01), Chiu et al.

Affiliated with

Also associated with

Rating

Two step etch back spin-on-glass process for semiconductor plana does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Two step etch back spin-on-glass process for semiconductor plana, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two step etch back spin-on-glass process for semiconductor plana will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1886462